module bitrev (
  input  sck,
  input  ss,
  input  mosi,
  output miso
);
  reg [7:0] counter;
  reg [7:0] data;

  wire reset = ss;

  always @(posedge sck or posedge reset) begin
    if (reset) counter <= 8'd0;
    else counter <= counter < 8'd15 ? counter + 1 : 8'd0;
  end

  always @(posedge sck or posedge reset) begin
    if (reset) data <= 8'd0;
    else if (counter < 8'd8) begin
      data <= { data[6:0] , mosi };
    end
    else if (counter == 8'd8) begin
      data <= data;
    end
    else begin
      data <= { 1'b0, data[7:1]};
    end
  end

  assign miso = ss ? 1'b1 : data[0];
endmodule
